Static Timing Analysis

Project : Internet PSoC Breakout
Build Time : 08/30/21 17:58:40
Device : CY8C5467LTI-LP003
Temperature : -40C - 85/125C
VDDA : 3.30
VDDABUF : 3.30
VDDD : 3.30
VDDIO0 : 3.30
VDDIO1 : 3.30
VDDIO2 : 3.30
VDDIO3 : 3.30
VUSB : 3.30
Voltage : 3.3
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 36.000 MHz 36.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 36.000 MHz 36.000 MHz N/A
ENC28J60_SPIM_IntClock CyMASTER_CLK 18.000 MHz 18.000 MHz 53.559 MHz
Clock_1 CyMASTER_CLK 1.000 kHz 1.000 kHz 34.168 MHz
CyPLL_OUT CyPLL_OUT 36.000 MHz 36.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 1e+006ns(1 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_581_1/q Net_581_31/main_7 34.168 MHz 29.267 999970.733
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(0,2) 1 Net_581_1 Net_581_1/clock_0 Net_581_1/q 1.250
Route 1 Net_581_1 Net_581_1/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 3.898
macrocell12 U(0,3) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 4.192
macrocell11 U(0,1) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 3.681
macrocell10 U(0,0) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q Net_581_31/main_7 2.686
macrocell26 U(1,0) 1 Net_581_31 SETUP 3.510
Clock Skew 0.000
Net_581_1/q Net_581_30/main_6 34.168 MHz 29.267 999970.733
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(0,2) 1 Net_581_1 Net_581_1/clock_0 Net_581_1/q 1.250
Route 1 Net_581_1 Net_581_1/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 3.898
macrocell12 U(0,3) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 4.192
macrocell11 U(0,1) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 3.681
macrocell10 U(0,0) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q Net_581_30/main_6 2.686
macrocell27 U(1,0) 1 Net_581_30 SETUP 3.510
Clock Skew 0.000
Net_581_1/q Net_581_29/main_5 34.168 MHz 29.267 999970.733
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(0,2) 1 Net_581_1 Net_581_1/clock_0 Net_581_1/q 1.250
Route 1 Net_581_1 Net_581_1/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 3.898
macrocell12 U(0,3) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 4.192
macrocell11 U(0,1) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 3.681
macrocell10 U(0,0) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q Net_581_29/main_5 2.686
macrocell28 U(1,0) 1 Net_581_29 SETUP 3.510
Clock Skew 0.000
Net_581_1/q Net_581_28/main_4 34.168 MHz 29.267 999970.733
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(0,2) 1 Net_581_1 Net_581_1/clock_0 Net_581_1/q 1.250
Route 1 Net_581_1 Net_581_1/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 3.898
macrocell12 U(0,3) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 4.192
macrocell11 U(0,1) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 3.681
macrocell10 U(0,0) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q Net_581_28/main_4 2.686
macrocell29 U(1,0) 1 Net_581_28 SETUP 3.510
Clock Skew 0.000
Net_581_1/q Net_581_27/main_3 34.180 MHz 29.257 999970.743
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(0,2) 1 Net_581_1 Net_581_1/clock_0 Net_581_1/q 1.250
Route 1 Net_581_1 Net_581_1/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 3.898
macrocell12 U(0,3) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 4.192
macrocell11 U(0,1) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 3.681
macrocell10 U(0,0) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q Net_581_27/main_3 2.676
macrocell30 U(1,0) 1 Net_581_27 SETUP 3.510
Clock Skew 0.000
Net_581_1/q Net_581_26/main_2 34.180 MHz 29.257 999970.743
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(0,2) 1 Net_581_1 Net_581_1/clock_0 Net_581_1/q 1.250
Route 1 Net_581_1 Net_581_1/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 3.898
macrocell12 U(0,3) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 4.192
macrocell11 U(0,1) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 3.681
macrocell10 U(0,0) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q Net_581_26/main_2 2.676
macrocell31 U(1,0) 1 Net_581_26 SETUP 3.510
Clock Skew 0.000
Net_581_1/q Net_581_25/main_1 34.180 MHz 29.257 999970.743
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(0,2) 1 Net_581_1 Net_581_1/clock_0 Net_581_1/q 1.250
Route 1 Net_581_1 Net_581_1/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 3.898
macrocell12 U(0,3) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 4.192
macrocell11 U(0,1) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 3.681
macrocell10 U(0,0) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q Net_581_25/main_1 2.676
macrocell32 U(1,0) 1 Net_581_25 SETUP 3.510
Clock Skew 0.000
Net_581_1/q Net_581_24/main_0 34.180 MHz 29.257 999970.743
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(0,2) 1 Net_581_1 Net_581_1/clock_0 Net_581_1/q 1.250
Route 1 Net_581_1 Net_581_1/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 3.898
macrocell12 U(0,3) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 4.192
macrocell11 U(0,1) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 3.681
macrocell10 U(0,0) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q Net_581_24/main_0 2.676
macrocell33 U(1,0) 1 Net_581_24 SETUP 3.510
Clock Skew 0.000
Net_581_4/q Net_581_31/main_7 34.217 MHz 29.225 999970.775
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell52 U(0,2) 1 Net_581_4 Net_581_4/clock_0 Net_581_4/q 1.250
Route 1 Net_581_4 Net_581_4/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_3 3.856
macrocell12 U(0,3) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_3 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 4.192
macrocell11 U(0,1) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 3.681
macrocell10 U(0,0) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q Net_581_31/main_7 2.686
macrocell26 U(1,0) 1 Net_581_31 SETUP 3.510
Clock Skew 0.000
Net_581_4/q Net_581_30/main_6 34.217 MHz 29.225 999970.775
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell52 U(0,2) 1 Net_581_4 Net_581_4/clock_0 Net_581_4/q 1.250
Route 1 Net_581_4 Net_581_4/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_3 3.856
macrocell12 U(0,3) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_3 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 4.192
macrocell11 U(0,1) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_16\/q \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 3.681
macrocell10 U(0,0) 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/main_8 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q 3.350
Route 1 \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\ \BasicCounter:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_24\/q Net_581_30/main_6 2.686
macrocell27 U(1,0) 1 Net_581_30 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 55.5556ns(18 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\ENC28J60:SPIM:BSPIM:sR8:Dp:u0\/so_comb \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_1 53.559 MHz 18.671 36.885
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,4) 1 \ENC28J60:SPIM:BSPIM:sR8:Dp:u0\ \ENC28J60:SPIM:BSPIM:sR8:Dp:u0\/clock \ENC28J60:SPIM:BSPIM:sR8:Dp:u0\/so_comb 5.360
Route 1 \ENC28J60:SPIM:BSPIM:mosi_from_dp\ \ENC28J60:SPIM:BSPIM:sR8:Dp:u0\/so_comb \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\/main_3 3.534
macrocell13 U(1,3) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\/main_3 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\/q \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_1 2.917
macrocell20 U(0,4) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:sR8:Dp:u0\/so_comb \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_0 58.319 MHz 17.147 38.409
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,4) 1 \ENC28J60:SPIM:BSPIM:sR8:Dp:u0\ \ENC28J60:SPIM:BSPIM:sR8:Dp:u0\/clock \ENC28J60:SPIM:BSPIM:sR8:Dp:u0\/so_comb 5.360
Route 1 \ENC28J60:SPIM:BSPIM:mosi_from_dp\ \ENC28J60:SPIM:BSPIM:sR8:Dp:u0\/so_comb \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/main_3 2.621
macrocell1 U(1,4) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/main_3 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/q \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_0 2.306
macrocell20 U(0,4) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:BitCounter\/count_4 \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_0 65.117 MHz 15.357 40.199
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \ENC28J60:SPIM:BSPIM:BitCounter\ \ENC28J60:SPIM:BSPIM:BitCounter\/clock \ENC28J60:SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \ENC28J60:SPIM:BSPIM:count_4\ \ENC28J60:SPIM:BSPIM:BitCounter\/count_4 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/main_4 4.251
macrocell1 U(1,4) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/main_4 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/q \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_0 2.306
macrocell20 U(0,4) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \ENC28J60:SPIM:BSPIM:RxStsReg\/status_6 65.621 MHz 15.239 40.317
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,4) 1 \ENC28J60:SPIM:BSPIM:sR8:Dp:u0\ \ENC28J60:SPIM:BSPIM:sR8:Dp:u0\/clock \ENC28J60:SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 3.580
Route 1 \ENC28J60:SPIM:BSPIM:rx_status_4\ \ENC28J60:SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \ENC28J60:SPIM:BSPIM:rx_status_6\/main_5 3.615
macrocell9 U(1,3) 1 \ENC28J60:SPIM:BSPIM:rx_status_6\ \ENC28J60:SPIM:BSPIM:rx_status_6\/main_5 \ENC28J60:SPIM:BSPIM:rx_status_6\/q 3.350
Route 1 \ENC28J60:SPIM:BSPIM:rx_status_6\ \ENC28J60:SPIM:BSPIM:rx_status_6\/q \ENC28J60:SPIM:BSPIM:RxStsReg\/status_6 4.194
statusicell2 U(1,3) 1 \ENC28J60:SPIM:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:BitCounter\/count_4 \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_1 65.660 MHz 15.230 40.326
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \ENC28J60:SPIM:BSPIM:BitCounter\ \ENC28J60:SPIM:BSPIM:BitCounter\/clock \ENC28J60:SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \ENC28J60:SPIM:BSPIM:count_4\ \ENC28J60:SPIM:BSPIM:BitCounter\/count_4 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\/main_4 3.513
macrocell13 U(1,3) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\/main_4 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\/q \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_1 2.917
macrocell20 U(0,4) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:state_1\/q \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_1 65.716 MHz 15.217 40.339
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(1,4) 1 \ENC28J60:SPIM:BSPIM:state_1\ \ENC28J60:SPIM:BSPIM:state_1\/clock_0 \ENC28J60:SPIM:BSPIM:state_1\/q 1.250
Route 1 \ENC28J60:SPIM:BSPIM:state_1\ \ENC28J60:SPIM:BSPIM:state_1\/q \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\/main_1 4.190
macrocell13 U(1,3) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\/main_1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split_1\/q \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_1 2.917
macrocell20 U(0,4) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:BitCounter\/count_1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_0 66.397 MHz 15.061 40.495
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \ENC28J60:SPIM:BSPIM:BitCounter\ \ENC28J60:SPIM:BSPIM:BitCounter\/clock \ENC28J60:SPIM:BSPIM:BitCounter\/count_1 1.940
Route 1 \ENC28J60:SPIM:BSPIM:count_1\ \ENC28J60:SPIM:BSPIM:BitCounter\/count_1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/main_7 3.955
macrocell1 U(1,4) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/main_7 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/q \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_0 2.306
macrocell20 U(0,4) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:state_0\/q \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_0 66.507 MHz 15.036 40.520
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,3) 1 \ENC28J60:SPIM:BSPIM:state_0\ \ENC28J60:SPIM:BSPIM:state_0\/clock_0 \ENC28J60:SPIM:BSPIM:state_0\/q 1.250
Route 1 \ENC28J60:SPIM:BSPIM:state_0\ \ENC28J60:SPIM:BSPIM:state_0\/q \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/main_2 4.620
macrocell1 U(1,4) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/main_2 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/q \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_0 2.306
macrocell20 U(0,4) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:BitCounter\/count_3 \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_0 66.849 MHz 14.959 40.597
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \ENC28J60:SPIM:BSPIM:BitCounter\ \ENC28J60:SPIM:BSPIM:BitCounter\/clock \ENC28J60:SPIM:BSPIM:BitCounter\/count_3 1.940
Route 1 \ENC28J60:SPIM:BSPIM:count_3\ \ENC28J60:SPIM:BSPIM:BitCounter\/count_3 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/main_5 3.853
macrocell1 U(1,4) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/main_5 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/q \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_0 2.306
macrocell20 U(0,4) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:BitCounter\/count_2 \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_0 66.854 MHz 14.958 40.598
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \ENC28J60:SPIM:BSPIM:BitCounter\ \ENC28J60:SPIM:BSPIM:BitCounter\/clock \ENC28J60:SPIM:BSPIM:BitCounter\/count_2 1.940
Route 1 \ENC28J60:SPIM:BSPIM:count_2\ \ENC28J60:SPIM:BSPIM:BitCounter\/count_2 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/main_6 3.852
macrocell1 U(1,4) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/main_6 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\ \ENC28J60:SPIM:BSPIM:mosi_pre_reg_split\/q \ENC28J60:SPIM:BSPIM:mosi_pre_reg\/main_0 2.306
macrocell20 U(0,4) 1 \ENC28J60:SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Net_581_5/q Net_581_7/main_1 3.537
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell51 U(0,3) 1 Net_581_5 Net_581_5/clock_0 Net_581_5/q 1.250
Route 1 Net_581_5 Net_581_5/q Net_581_7/main_1 2.287
macrocell49 U(0,3) 1 Net_581_7 HOLD 0.000
Clock Skew 0.000
Net_581_5/q Net_581_6/main_0 3.537
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell51 U(0,3) 1 Net_581_5 Net_581_5/clock_0 Net_581_5/q 1.250
Route 1 Net_581_5 Net_581_5/q Net_581_6/main_0 2.287
macrocell50 U(0,3) 1 Net_581_6 HOLD 0.000
Clock Skew 0.000
Net_581_0/q Net_581_3/main_2 3.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell56 U(1,4) 1 Net_581_0 Net_581_0/clock_0 Net_581_0/q 1.250
Route 1 Net_581_0 Net_581_0/q Net_581_3/main_2 2.290
macrocell53 U(0,4) 1 Net_581_3 HOLD 0.000
Clock Skew 0.000
Net_581_6/q Net_581_7/main_0 3.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell50 U(0,3) 1 Net_581_6 Net_581_6/clock_0 Net_581_6/q 1.250
Route 1 Net_581_6 Net_581_6/q Net_581_7/main_0 2.308
macrocell49 U(0,3) 1 Net_581_7 HOLD 0.000
Clock Skew 0.000
Net_581_8/q Net_581_9/main_0 3.561
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(0,4) 1 Net_581_8 Net_581_8/clock_0 Net_581_8/q 1.250
Route 1 Net_581_8 Net_581_8/q Net_581_9/main_0 2.311
macrocell48 U(0,4) 1 Net_581_9 HOLD 0.000
Clock Skew 0.000
Net_581_27/q Net_581_31/main_3 3.763
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(1,0) 1 Net_581_27 Net_581_27/clock_0 Net_581_27/q 1.250
Route 1 Net_581_27 Net_581_27/q Net_581_31/main_3 2.513
macrocell26 U(1,0) 1 Net_581_31 HOLD 0.000
Clock Skew 0.000
Net_581_27/q Net_581_30/main_2 3.763
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(1,0) 1 Net_581_27 Net_581_27/clock_0 Net_581_27/q 1.250
Route 1 Net_581_27 Net_581_27/q Net_581_30/main_2 2.513
macrocell27 U(1,0) 1 Net_581_30 HOLD 0.000
Clock Skew 0.000
Net_581_27/q Net_581_29/main_1 3.763
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(1,0) 1 Net_581_27 Net_581_27/clock_0 Net_581_27/q 1.250
Route 1 Net_581_27 Net_581_27/q Net_581_29/main_1 2.513
macrocell28 U(1,0) 1 Net_581_29 HOLD 0.000
Clock Skew 0.000
Net_581_27/q Net_581_28/main_0 3.763
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(1,0) 1 Net_581_27 Net_581_27/clock_0 Net_581_27/q 1.250
Route 1 Net_581_27 Net_581_27/q Net_581_28/main_0 2.513
macrocell29 U(1,0) 1 Net_581_28 HOLD 0.000
Clock Skew 0.000
Net_581_29/q Net_581_31/main_1 3.787
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(1,0) 1 Net_581_29 Net_581_29/clock_0 Net_581_29/q 1.250
Route 1 Net_581_29 Net_581_29/q Net_581_31/main_1 2.537
macrocell26 U(1,0) 1 Net_581_31 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\ENC28J60:SPIM:BSPIM:BitCounter\/count_3 \ENC28J60:SPIM:BSPIM:state_2\/main_4 3.426
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \ENC28J60:SPIM:BSPIM:BitCounter\ \ENC28J60:SPIM:BSPIM:BitCounter\/clock \ENC28J60:SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \ENC28J60:SPIM:BSPIM:count_3\ \ENC28J60:SPIM:BSPIM:BitCounter\/count_3 \ENC28J60:SPIM:BSPIM:state_2\/main_4 2.806
macrocell15 U(1,3) 1 \ENC28J60:SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:BitCounter\/count_3 \ENC28J60:SPIM:BSPIM:state_0\/main_4 3.426
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \ENC28J60:SPIM:BSPIM:BitCounter\ \ENC28J60:SPIM:BSPIM:BitCounter\/clock \ENC28J60:SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \ENC28J60:SPIM:BSPIM:count_3\ \ENC28J60:SPIM:BSPIM:BitCounter\/count_3 \ENC28J60:SPIM:BSPIM:state_0\/main_4 2.806
macrocell17 U(1,3) 1 \ENC28J60:SPIM:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:BitCounter\/count_3 \ENC28J60:SPIM:BSPIM:ld_ident\/main_4 3.426
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \ENC28J60:SPIM:BSPIM:BitCounter\ \ENC28J60:SPIM:BSPIM:BitCounter\/clock \ENC28J60:SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \ENC28J60:SPIM:BSPIM:count_3\ \ENC28J60:SPIM:BSPIM:BitCounter\/count_3 \ENC28J60:SPIM:BSPIM:ld_ident\/main_4 2.806
macrocell23 U(1,3) 1 \ENC28J60:SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:BitCounter\/count_2 \ENC28J60:SPIM:BSPIM:state_2\/main_5 3.428
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \ENC28J60:SPIM:BSPIM:BitCounter\ \ENC28J60:SPIM:BSPIM:BitCounter\/clock \ENC28J60:SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \ENC28J60:SPIM:BSPIM:count_2\ \ENC28J60:SPIM:BSPIM:BitCounter\/count_2 \ENC28J60:SPIM:BSPIM:state_2\/main_5 2.808
macrocell15 U(1,3) 1 \ENC28J60:SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:BitCounter\/count_2 \ENC28J60:SPIM:BSPIM:state_0\/main_5 3.428
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \ENC28J60:SPIM:BSPIM:BitCounter\ \ENC28J60:SPIM:BSPIM:BitCounter\/clock \ENC28J60:SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \ENC28J60:SPIM:BSPIM:count_2\ \ENC28J60:SPIM:BSPIM:BitCounter\/count_2 \ENC28J60:SPIM:BSPIM:state_0\/main_5 2.808
macrocell17 U(1,3) 1 \ENC28J60:SPIM:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:BitCounter\/count_2 \ENC28J60:SPIM:BSPIM:ld_ident\/main_5 3.428
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \ENC28J60:SPIM:BSPIM:BitCounter\ \ENC28J60:SPIM:BSPIM:BitCounter\/clock \ENC28J60:SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \ENC28J60:SPIM:BSPIM:count_2\ \ENC28J60:SPIM:BSPIM:BitCounter\/count_2 \ENC28J60:SPIM:BSPIM:ld_ident\/main_5 2.808
macrocell23 U(1,3) 1 \ENC28J60:SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:BitCounter\/count_0 \ENC28J60:SPIM:BSPIM:state_2\/main_7 3.443
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \ENC28J60:SPIM:BSPIM:BitCounter\ \ENC28J60:SPIM:BSPIM:BitCounter\/clock \ENC28J60:SPIM:BSPIM:BitCounter\/count_0 0.620
Route 1 \ENC28J60:SPIM:BSPIM:count_0\ \ENC28J60:SPIM:BSPIM:BitCounter\/count_0 \ENC28J60:SPIM:BSPIM:state_2\/main_7 2.823
macrocell15 U(1,3) 1 \ENC28J60:SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:BitCounter\/count_0 \ENC28J60:SPIM:BSPIM:state_0\/main_7 3.443
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \ENC28J60:SPIM:BSPIM:BitCounter\ \ENC28J60:SPIM:BSPIM:BitCounter\/clock \ENC28J60:SPIM:BSPIM:BitCounter\/count_0 0.620
Route 1 \ENC28J60:SPIM:BSPIM:count_0\ \ENC28J60:SPIM:BSPIM:BitCounter\/count_0 \ENC28J60:SPIM:BSPIM:state_0\/main_7 2.823
macrocell17 U(1,3) 1 \ENC28J60:SPIM:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:BitCounter\/count_0 \ENC28J60:SPIM:BSPIM:ld_ident\/main_7 3.443
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \ENC28J60:SPIM:BSPIM:BitCounter\ \ENC28J60:SPIM:BSPIM:BitCounter\/clock \ENC28J60:SPIM:BSPIM:BitCounter\/count_0 0.620
Route 1 \ENC28J60:SPIM:BSPIM:count_0\ \ENC28J60:SPIM:BSPIM:BitCounter\/count_0 \ENC28J60:SPIM:BSPIM:ld_ident\/main_7 2.823
macrocell23 U(1,3) 1 \ENC28J60:SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\ENC28J60:SPIM:BSPIM:cnt_enable\/q \ENC28J60:SPIM:BSPIM:cnt_enable\/main_3 3.545
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(1,2) 1 \ENC28J60:SPIM:BSPIM:cnt_enable\ \ENC28J60:SPIM:BSPIM:cnt_enable\/clock_0 \ENC28J60:SPIM:BSPIM:cnt_enable\/q 1.250
macrocell24 U(1,2) 1 \ENC28J60:SPIM:BSPIM:cnt_enable\ \ENC28J60:SPIM:BSPIM:cnt_enable\/q \ENC28J60:SPIM:BSPIM:cnt_enable\/main_3 2.295
macrocell24 U(1,2) 1 \ENC28J60:SPIM:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ ENC28J60_SPIM_IntClock
Source Destination Delay (ns)
MISO(0)_PAD \ENC28J60:SPIM:BSPIM:sR8:Dp:u0\/route_si 18.293
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 MISO(0)_PAD MISO(0)_PAD MISO(0)/pad_in 0.000
iocell3 P15[0] 1 MISO(0) MISO(0)/pad_in MISO(0)/fb 6.334
Route 1 Net_438 MISO(0)/fb \ENC28J60:SPIM:BSPIM:sR8:Dp:u0\/route_si 8.459
datapathcell1 U(1,4) 1 \ENC28J60:SPIM:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\ENC28J60:SS_HOLD:Sync:ctrl_reg\/control_0 CS(0)_PAD 32.669
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(1,3) 1 \ENC28J60:SS_HOLD:Sync:ctrl_reg\ \ENC28J60:SS_HOLD:Sync:ctrl_reg\/busclk \ENC28J60:SS_HOLD:Sync:ctrl_reg\/control_0 2.050
Route 1 \ENC28J60:Net_166\ \ENC28J60:SS_HOLD:Sync:ctrl_reg\/control_0 Net_437/main_1 2.937
macrocell3 U(0,2) 1 Net_437 Net_437/main_1 Net_437/q 3.350
Route 1 Net_437 Net_437/q CS(0)/pin_input 7.365
iocell4 P12[7] 1 CS(0) CS(0)/pin_input CS(0)/pad_out 16.967
Route 1 CS(0)_PAD CS(0)/pad_out CS(0)_PAD 0.000
Clock Clock path delay 0.000
\ENC28J60:RESET:Sync:ctrl_reg\/control_0 RST(0)_PAD 30.532
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,4) 1 \ENC28J60:RESET:Sync:ctrl_reg\ \ENC28J60:RESET:Sync:ctrl_reg\/busclk \ENC28J60:RESET:Sync:ctrl_reg\/control_0 2.050
Route 1 \ENC28J60:Net_6\ \ENC28J60:RESET:Sync:ctrl_reg\/control_0 Net_439/main_0 2.308
macrocell2 U(0,4) 1 Net_439 Net_439/main_0 Net_439/q 3.350
Route 1 Net_439 Net_439/q RST(0)/pin_input 6.604
iocell2 P12[6] 1 RST(0) RST(0)/pin_input RST(0)/pad_out 16.220
Route 1 RST(0)_PAD RST(0)/pad_out RST(0)_PAD 0.000
Clock Clock path delay 0.000
+ ENC28J60_SPIM_IntClock
Source Destination Delay (ns)
\ENC28J60:SPIM:BSPIM:state_1\/q MOSI(0)_PAD 36.086
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(1,4) 1 \ENC28J60:SPIM:BSPIM:state_1\ \ENC28J60:SPIM:BSPIM:state_1\/clock_0 \ENC28J60:SPIM:BSPIM:state_1\/q 1.250
Route 1 \ENC28J60:SPIM:BSPIM:state_1\ \ENC28J60:SPIM:BSPIM:state_1\/q Net_435/main_1 6.072
macrocell6 U(1,1) 1 Net_435 Net_435/main_1 Net_435/q 3.350
Route 1 Net_435 Net_435/q MOSI(0)/pin_input 6.361
iocell6 P15[7] 1 MOSI(0) MOSI(0)/pin_input MOSI(0)/pad_out 19.053
Route 1 MOSI(0)_PAD MOSI(0)/pad_out MOSI(0)_PAD 0.000
Clock Clock path delay 0.000
Net_436/q SCK(0)_PAD 26.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(1,2) 1 Net_436 Net_436/clock_0 Net_436/q 1.250
Route 1 Net_436 Net_436/q SCK(0)/pin_input 6.177
iocell5 P15[6] 1 SCK(0) SCK(0)/pin_input SCK(0)/pad_out 19.129
Route 1 SCK(0)_PAD SCK(0)/pad_out SCK(0)_PAD 0.000
Clock Clock path delay 0.000